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semiconductor 4-192 march 1997 82c37a cmos high performance programmable dma controller features ? compatible with the nmos 8237a ? four independent maskable channels with autoinitial- ization capability ? cascadable to any number of channels ? high speed data transfers: - up to 4mbytes/sec with 8mhz clock - up to 6.25mbytes/sec with 12.5mhz clock ? memory-to-memory transfers ? static cmos design permits low power operation - iccsb = 10 m a maximum - iccop = 2ma/mhz maximum ? fully ttl/cmos compatible ? internal registers may be read from software description the 82c37a is an enhanced version of the industry standard 8237a direct memory access (dma) controller, fabricated using harris advanced 2 micron cmos process. pin compatible with nmos designs, the 82c37a offers increased functionality, improved performance, and dramatically reduced power consumption. the fully static design permits gated clock operation for even further reduction of power. the 82c37a controller can improve system performance by allowing external devices to transfer data directly to or from system memory. memory-to-memory transfer capability is also provided, along with a memory block initialization fea- ture. dma requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for ?exible operation. the 82c37a is designed to be used with an external address latch, such as the 82c82, to demultiplex the most signi?cant 8-bits of address. the 82c37a can be used with industry standard microprocessors such as 80c286, 80286, 80c86, 80c88, 8086, 8088, 8085, z80, nsc800, 80186 and others. multimode programmability allows the user to select from three basic types of dma services, and recon?guration under program control is possible even with the clock to the controller stopped. each channel has a full 64k address and word count range, and may be programmed to autoinitialize these registers following dma termination (end of process). ordering information part number package temperature range pkg. no. 5mhz 8mhz 12.5mhz cp82c37a-5 cp82c37a cp82c37a-12 40 ld pdip 0 o c to +70 o c e40.6 ip82c37a-5 ip82c37a ip82c37a-12 -40 o c to +85 o c e40.6 cs82c37a-5 cs82c37a cs82c37a-12 44 ld plcc 0 o c to +70 o c n44.65 is82c37a-5 is82c37a is82c37a-12 -40 o c to +85 o c n44.65 cd82c37a-5 cd82c37a cd82c37a-12 40 ld cerdip 0 o c to +70 o c f40.6 id82c37a-5 id82c37a id82c37a-12 -40 o c to +85 o c f40.6 md82c37a-5/b md82c37a/b md82c37a-12/b -55 o c to +125 o c f40.6 5962-9054301mqa 5962-9054302mqa 5962-9054303mqa smd# f40.6 mr82c37a-5/b mr82c37a/b mr82c37a-12/b 44 pad clcc -55 o c to +125 o c j44.a 5962-9054301mxa 5962-9054302mxa 5962-9054303mxa smd# j44.a caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1997 file number 2967.1
4-193 82c37a block diagram pinouts 82c37a (pdip/cerdip) top view 82c37a (clcc/plcc) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 ior io w memr memw nc ready hlda adstb aen hrq cs clk reset dack2 dack3 dreq3 dreq2 dreq1 dreq0 (gnd) vss 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 a7 a6 a5 a4 eop a3 a2 a1 a0 vcc db0 db1 db2 db3 db4 dack0 dack1 db5 db6 db7 14 13 12 11 10 9 8 7 17 16 15 2 5 30 35 39 38 37 36 33 34 32 31 29 4 6 3 1 40 41 42 43 44 28 27 26 25 24 23 22 21 20 19 18 cs dack2 nc nc clk hrq nc a3 a2 a1 a0 vcc db0 db1 db2 db3 nc db4 ready nc a7 a6 a5 memw a4 eop dack3 dreq3 dreq2 dreq1 dreq0 gnd db5 dack1 db7 dack0 db6 memr adstb aen io w reset hlda ior a4 - a7 eop reset cs ready clk aen adstb memr memw ior io w timing and control dreq0 - hlda hrq dack0 - priority encoder and rotating priority logic dack3 4 dreq3 4 command (8) mask (4) request (4) mode (4 x 6) status (8) temporary (8) internal data bus decrementor count reg (16) temp word inc/decrementor reg (16) temp address buffer io 16-bit bus read buffer address base (16) word base count (16) read write buffer address current (16) word current count (16) 16-bit bus buffer write buffer read a8 - a15 buffer output control command d0 - d1 a0 - a3 buffer io db0 - db7
4-194 82c37a pin description symbol pin number type description v cc 31 v cc : is the +5v power supply pin. a 0.1 m f capacitor between pins 31 and 20 is recommended for decoupling. gnd 20 ground clk 12 i clock input: the clock input is used to generate the timing signals which control 82c37a operations. this input may be driven from dc to 12.5mhz for the 82c37a-12, from dc to 8mhz for the 82c37a, or from dc to 5mhz for the 82c37a-5. the clock may be stopped in either state for standby operation. cs 11 i chip select: chip select is an active low input used to enable the controller onto the data bus for cpu communications. reset 13 i reset: this is an active high input which clears the command, status, request, and temporary registers, the first/last flip-flop, and the mode register counter. the mask register is set to ignore requests. following a reset, the controller is in an idle cycle. ready 6 i ready: this signal can be used to extend the memory read and write pulses from the 82c37a to accommodate slow memories or i/o devices. ready must not make transitions during its speci?ed set-up and hold times. see figure 12 for timing. ready is ignored in verify transfer mode. hlda 7 i hold acknowledge: the active high hold acknowledge from the cpu indicates that it has relinquished control of the system busses. hlda is a synchronous input and must not transition during its speci?ed set-up time. there is an implied hold time (hlda inactive) of tch from the rising edge of clk, during which time hlda must not transition. dreq0- dreq3 16-19 i dma request: the dma request (dreq) lines are individual asynchronous channel request inputs used by peripheral circuits to obtain dma service. in fixed priority, dreq0 has the highest priority and dreq3 has the lowest priority. a request is generated by activating the dreq line of a channel. dack will acknowledge the recognition of a dreq signal. polarity of dreq is programmable. reset initializes these lines to active high. dreq must be maintained until the corresponding dack goes active. dreq will not be recognized while the clock is stopped. unused dreq inputs should be pulled high or low (inactive) and the corresponding mask bit set. db0-db7 21-23 26-30 i/o data bus: the data bus lines are bidirectional three-state signals connected to the system data bus. the outputs are enabled in the program condition during the i/o read to output the contents of a register to the cpu. the outputs are disabled and the inputs are read during an i/o write cycle when the cpu is programming the 82c37a control registers. during dma cycles, the most signi?- cant 8-bits of the address are output onto the data bus to be strobed into an external latch by adstb. in memory-to-memory operations, data from the memory enters the 82c37a on the data bus during the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new memory location. ior 1 i/o i/o read: i/o read is a bidirectional active low three-state line. in the idle cycle, it is an input con- trol signal used by the cpu to read the control registers. in the active cycle, it is an output control signal used by the 82c37a to access data from the peripheral during a dma write transfer. io w 2 i/o i/o write: i/o write is a bidirectional active low three-state line. in the idle cycle, it is an input con- trol signal used by the cpu to load information into the 82c37a. in the active cycle, it is an output control signal used by the 82c37a to load data to the peripheral during a dma read transfer.
4-195 82c37a eop 36 i/o end of process: end of process ( eop) is an active low bidirectional signal. information concerning the completion of dma services is available at the bidirectional eop pin. the 82c37a allows an external signal to terminate an active dma service by pulling the eop pin low. a pulse is generated by the 82c37a when terminal count (tc) for any channel is reached, except for channel 0 in memory-to-memory mode. during memory-to-memory transfers, eop will be output when the tc for channel 1 occurs. the eop pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor to v cc . when an eop pulse occurs, whether internally or externally generated, the 82c37a will terminate the service, and if autoinitialize is enabled, the base registers will be written to the current registers of that channel. the mask bit and tc bit in the status word will be set for the currently active channel by eop unless the channel is programmed for autoinitialize. in that case, the mask bit remains clear. a0-a3 32-35 i/o address: the four least signi?cant address lines are bidirectional three-state signals. in the idle cycle, they are inputs and are used by the 82c37a to address the control register to be loaded or read. in the active cycle, they are outputs and provide the lower 4-bits of the output address. a4-a7 37-40 o address: the four most signi?cant address lines are three-state outputs and provide 4-bits of address. these lines are enabled only during the dma service. hrq 10 o hold request: the hold request (hrq) output is used to request control of the system bus. when a dreq occurs and the corresponding mask bit is clear, or a software dma request is made, the 82c37a issues hrq. the hlda signal then informs the controller when access to the system busses is permitted. for stand-alone operation where the 82c37a always controls the busses, hrq may be tied to hlda. this will result in one s0 state before the transfer. dack0- dack3 14, 15 24, 25 o dma acknowledge: dma acknowledge is used to notify the individual peripherals when one has been granted a dma cycle. the sense of these lines is programmable. reset initializes them to active low. aen 9 o address enable: address enable enables the 8-bit latch containing the upper 8 address bits onto the system address bus. aen can also be used to disable other system bus drivers during dma transfers. aen is active high. adstb 8 o address strobe: this is an active high signal used to control latching of the upper address byte. it will drive directly the strobe input of external transparent octal latches, such as the 82c82. during block operations, adstb will only be issued when the upper address byte must be updated, thus speeding operation through elimination of s1 states. adstb timing is referenced to the falling edge of the 82c37a clock. memr 3 o memory read: the memory read signal is an active low three-state output used to access data from the selected memory location during a dma read or a memory-to-memory transfer. memw 4 o memory write: the memory write signal is an active low three-state output used to write data to the selected memory location during a dma write or a memory-to-memory transfer. nc 5 no connect: pin 5 is open and should not be tested for continuity. pin description (continued) symbol pin number type description
4-196 82c37a functional description the 82c37a direct memory access controller is designed to improve the data transfer rate in systems which must transfer data from an i/o device to memory, or move a block of memory to an i/o device. it will also perform memory-to- memory block moves, or ?ll a block of memory with data from a single location. operating modes are provided to handle single byte transfers as well as discontinuous data streams, which allows the 82c37a to control data movement with software transparency. the dma controller is a state-driven address and control signal generator, which permits data to be transferred directly from an i/o device to memory or vice versa without ever being stored in a temporary register. this can greatly increase the data transfer rate for sequential operations, compared with processor move or repeated string instructions. memory-to-memory operations require temporary internal storage of the data byte between generation of the source and destination addresses, so memory-to-memory transfers take place at less than half the rate of i/o operations, but still much faster than with central processor techniques. the maximum data transfer rates obtainable with the 82c37a are shown in figure 1. the block diagram of the 82c37a is shown on page 2. the timing and control block, priority block, and internal registers are the main components. figure 2 lists the name and size of the internal registers. the timing and control block derives internal timing from clock input, and generates external control signals. the priority encoder block resolves priority contention between dma channels requesting service simultaneously. dma operation in a system, the 82c37a address and control outputs and data bus pins are basically connected in parallel with the system busses. an external latch is required for the upper address byte. while inactive, the controllers outputs are in a high impedance state. when activated by a dma request and bus control is relinquished by the host, the 82c37a drives the busses and generates the control signals to perform the data transfer. the operation performed by activating one of the four dma request inputs has previously been programmed into the controller via the command, mode, address, and word count registers. for example, if a block of data is to be transferred from ram to an i/o device, the starting address of the data is loaded into the 82c37a current and base address registers for a particular channel, and the length of the block is loaded into the channels word count register. the corresponding mode register is programmed for a memory-to-i/o operation (read transfer), and various options are selected by the command register and the other mode register bits. the channels mask bit is cleared to enable recognition of a dma request (dreq). the dreq can either be a hardware signal or a software command. once initiated, the block dma transfer will proceed as the controller outputs the data address, simultaneous memr and io w pulses, and selects an i/o device via the dma acknowledge (dack) outputs. the data byte ?ows directly from the ram to the i/o device. after each byte is transferred, the address is automatically incremented (or decremented) and the word count is decremented. the operation is then repeated for the next byte. the controller stops transferring data when the word count register under?ows, or an external eop is applied. to further understand 82c37a operation, the states generated by each clock cycle must be considered. the dma controller operates in two major cycles, active and idle. after being programmed, the controller is normally idle until a dma request occurs on an unmasked channel, or a software request is given. the 82c37a will then request control of the system busses and enter the active cycle. the active cycle is composed of several internal states, depending on what options have been selected and what type of operation has been requested. 82c37a transfer type 5mhz 8mhz 12.5mhz unit compressed 2.50 4.00 6.25 mbyte/sec normal i/o 1.67 2.67 4.17 mbyte/sec memory-to- memory 0.63 1.00 1.56 mbyte/sec figure 1. dma transfer rates name size number base address registers 16-bits 4 base word count registers 16-bits 4 current address registers 16-bits 4 current word count registers 16-bits 4 temporary address register 16-bits 1 temporary word count register 16-bits 1 status register 8-bits 1 command register 8-bits 1 temporary register 8-bits 1 mode registers 6-bits 4 mask register 4-bits 1 request register 4-bits 1 figure 2. 82c37a internal registers
4-197 82c37a the 82c37a can assume seven separate states, each composed of one full clock period. state i (si) is the idle state. it is entered when the 82c37a has no valid dma requests pending, at the end of a transfer sequence, or when a reset or master clear has occurred. while in si, the dma controller is inactive but may be in the program condition (being programmed by the processor). state 0 (s0) is the ?rst state of a dma service. the 82c37a has requested a hold but the processor has not yet returned an acknowledge. the 82c37a may still be programmed until it has received hlda from the cpu. an acknowledge from the cpu will signal the dma transfer may begin. s1, s2, s3, and s4 are the working state of the dma service. if more time is needed to complete a transfer than is available with normal timing, wait states (sw) can be inserted between s3 and s4 in normal transfers by the use of the ready line on the 82c37a. for compressed transfers, wait states can be inserted between s2 and s4. see timing figures 14 and 15. note that the data is transferred directly from the i/o device to memory (or vice versa) with ior and memw (or memr and io w) being active at the same time. the data is not read into or driven out of the 82c37a in i/o-to-memory or memory-to-i/o dma transfers. memory-to-memory transfers require a read-from and a write- to memory to complete each transfer. the states, which resemble the normal working states, use two-digit numbers for identi?cation. eight states are required for a single transfer. the ?rst four states (s11, s12, s13, s14) are used for the read-from-memory half and the last four state (s21, s22, s23, s24) for the write-to-memory half of the transfer. idle cycle when no channel is requesting service, the 82c37a will enter the idle cycle and perform si states. in this cycle, the 82c37a will sample the dreq lines on the falling edge of every clock cycle to determine if any channel is requesting a dma service. note that for standby operation where the clock has been stopped, dma requests will be ignored. the device will respond to cs (chip select), in case of an attempt by the microprocessor to write or read the internal registers of the 82c37a. when cs is low and hlda is low, the 82c37a enters the program condition. the cpu can now establish, change or inspect the internal de?nition of the part by read- ing from or writing to the internal registers. the 82c37a may be programmed with the clock stopped, pro- vided that hlda is low and at least one rising clock edge has occurred after hlda was driven low, so the controller is in an si state. address lines a0-a3 are inputs to the device and select which registers will be read or written. the ior and iow lines are used to select and time the read or write operations. due to the number and size of the internal registers, an internal ?ip-?op called the first/last flip-flop is used to generate an additional bit of address. the bit is used to determine the upper or lower byte of the 16-bit address and work count registers. the ?ip- ?op is reset by master clear or reset. separate software commands can also set or reset this ?ip-?op. special software commands can be executed by the 82c37a in the program condition. these commands are decoded as sets of addresses with cs, ior, and io w. the commands do not make use of the data bus. instructions include set and clear first/last flip-flop, master clear, clear mode register counter, and clear mask register. active cycle when the 82c37a is in the idle cycle, and a software request or an unmasked channel requests a dma service, the device will issue hrq to the microprocessor and enter the active cycle. it is in this cycle that the dma service will take place, in one of four modes: single transfer mode - in single transfer mode, the device is programmed to make one transfer only. the word count will be decremented and the address decremented or incremented following each transfer. when the word count rolls over from zero to ffffh, a terminal count bit in the status register is set, an eop pulse is generated, and the channel will autoinitialize if this option has been selected. if not programmed to autoinitialize, the mask bit will be set, along with the tc bit and eop pulse. dreq must be held active until dack becomes active. if dreq is held active throughout the single transfer, hrq will go inactive and release the bus to the system. it will again go active and, upon receipt of a new hlda, another single transfer will be performed, unless a higher priority channel takes over. in 8080a, 8085a, 80c88, or 80c86 systems, this will ensure one full machine cycle execution between dma transfers. details of timing between the 82c37a and other bus control protocols will depend upon the characteristics of the microprocessor involved. block transfer mode - in block transfer mode, the device is activated by dreq or software request and continues making transfers during the service until a tc, caused by word count going to ffffh, or an external end of process ( eop) is encountered. dreq need only be held active until dack becomes active. again, an autoinitialization will occur at the end of the service if the channel has been programmed for that option. demand transfer mode - in demand transfer mode the device continues making transfers until a tc or external eop is encountered, or until dreq goes inactive. thus, transfer may continue until the i/o device has exhausted its data capacity. after the i/o device has had a chance to catch up, the dma service is reestablished by means of a dreq. during the time between services when the microprocessor is allowed to oper- ate, the intermediate values of address and word count are stored in the 82c37a current address and current word count registers. higher priority channels may intervene in the demand process, once dreq has gone inactive. only an eop can cause an autoinitialization at the end of service. eop is generated either by tc or by an external signal. cascade mode - this mode is used to cascade more than one 82c37a for simple system expansion. the hrq and hlda signals from the additional 82c37a are connected to the dreq and dack signals respectively of a channel for
4-198 82c37a the initial 82c37a.this allows the dma requests of the additional device to propagate through the priority network circuitry of the preceding device. the priority chain is preserved and the new device must wait for its turn to acknowledge requests. since the cascade channel of the initial 82c37a is used only for prioritizing the additional device, it does not output an address or control signals of its own. these could con?ict with the outputs of the active chan- nel in the added device. the initial 82c37a will respond to dreq and generate dack but all other outputs except hrq will be disabled. an external eop will be ignored by the initial device, but will have the usual effect on the added device. figure 3 shows two additional devices cascaded with an initial device using two of the initial devices channels. this forms a two-level dma system. more 82c37as could be added at the second level by using the remaining channels of the ?rst level. additional devices can also be added by cascading into the channels of the second level devices, forming a third level. when programming cascaded controllers, start with the ?rst level device (closest to the microprocessor). after reset, the dack outputs are programmed to be active low and are held in the high state. if they are used to drive hlda directly, the second level device(s) cannot be programmed until dack polarity is selected as active high on the initial device. also, the initial devices mask bits function normally on cascaded channels, so they may be used to inhibit second- level services. transfer types each of the three active transfer modes can perform three dif- ferent types of transfers. these are read, write and verify. write transfers move data from an i/o device to the memory by activating memw and ior. read transfers move data from memory to an i/o device by activating memr and iow. verify transfers are pseudo-transfers. the 82c37a operates as in read or write transfers generating addresses and responding to eop, etc., however the memory and i/o control lines all remain inactive. verify mode is not permitted for memory-to-memory operation. ready is ignored during verify transfers. autoinitialize - by setting bit 4 in the mode register, a channel may be set up as an autoinitialize channel. during autoinitialization, the original values of the current address and current word count registers are automatically restored from the base address and base word count registers of the channel following eop. the base registers are loaded simultaneously with the current registers by the micropro- cessor and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize mode. following autoinitialization, the channel is ready to perform another dma service, without cpu intervention, as soon as a valid dreq is detected, or software request made. memory-to-memory - to perform block moves of data from one memory address space to another with minimum of program effort and time, the 82c37a includes a memory-to- memory transfer feature. setting bit 0 in the command register selects channels 0 and 1 to operate as memory-to- memory transfer channels. the transfer is initiated by setting the software or hardware dreq for channel 0. the 82c37a requests a dma service in the normal manner. after hlda is true, the device, using four-state transfers in block transfer mode, reads data from the memory. the channel 0 current address register is the source for the address used and is decremented or incremented in the normal manner. the data byte read from the memory is stored in the 82c37a internal temporary reg- ister. another four-state transfer moves the data to memory using the address in channel ones current address register and incrementing or decrementing it in the normal manner. the channel 1 current word count is decremented. when the word count of channel 1 decrements to ffffh, a tc is generated causing an eop output, terminating the service, and setting the channel 1 tc bit in the status register. the channel 1 mask bit will also be set, unless the channel 1 mode register is programmed for autoinitialization. channel 0 word count decrementing to ffffh will not set the channel 0 tc bit in the status register nor generate an eop, nor set the channel 0 mask bit in this mode. it will cause an autoinitialization of channel 0, if that option has been selected. if full autoinitialization for a memory-to-memory operation is desired, the channel 0 and channel 1 word counts must be set to equal values before the transfer begins. otherwise, if channel 0 under?ows before channel 1, it will autoinitialize and set the data source address back to the beginning of the block. if the channel 1 word count under?ows before channel 0, the memory-to-memory dma service will terminate, and channel 1 will autoinitialize but channel 0 will not. in memory-to-memory mode, channel 0 may be programmed to retain the same address for all transfers. this allows a single byte to be written to a block of memory. this channel 0 address hold feature is selected by setting bit 1 in the command register. the 82c37a will respond to external eop signals during memory-to-memory transfers, but will only relinquish the system busses after the transfer is complete (i.e. after an 80c86/88 micro- processor hrq hlda dreq dack dreq dack 1st level 82c37a hrq hlda 82c37a hrq hlda 82c37a additional devices 2nd level initial device figure 3. cascaded 82c37as
4-199 82c37a s24 state). it should be noted that an external eop cannot cause the channel 0 address and word count registers to autoinitialize, even if the mode register is programmed for autoinitialization. an external eop will autoinitialize the channel 1 registers, if so programmed. data comparators in block search schemes may use the eop input to terminate the service when a match is found. the timing of memory-to- memory transfers is found in figure 13. memory-to-memory operations can be detected as an active aen with no dack outputs. priority - the 82c37a has two types of priority encoding available as software selectable options. the ?rst is fixed priority which ?xes the channels in priority order based upon the descending value of their numbers. the channel with the lowest priority is 3 followed by 2, 1 and the highest priority channel, 0. after the recognition of any one channel for ser- vice, the other channels are prevented from interfering with the service until it is completed. the second scheme is rotating priority. the last channel to get service becomes the lowest priority channel with the others rotating accordingly. the next lower channel from the channel serviced has highest priority on the following request. priority rotates every time control of the system busses is returned to the processor. rotating priority with rotating priority in a single chip dma system, any device requesting service is guaranteed to be recognized after no more than three higher priority services have occurred. this prevents any one channel from monopolizing the system. regardless of which priority scheme is chosen, priority is evaluated every time a hlda is returned to the 82c37a. compressed timing - in order to achieve even greater throughput where system characteristics permit, the 82c37a can compress the transfer time to two clock cycles. from figure 12 it can be seen that state s3 is used to extend the access time of the read pulse. by removing state s3, the read pulse width is made equal to the write pulse width and a transfer consists only of state s2 to change the address and state s4 to perform the read/write. s1 states will still occur when a8-a15 need updating (see address generation). timing for compressed transfers is found in figure 15. eop will output in s2 if compressed timing is selected. compressed timing is not allowed for memory-to- memory transfers. address generation - in order to reduce pin count, the 82c37a multiplexes the eight higher order address bits on the data lines. state s1 is used to output the higher order address bits to an external latch from which they may be placed on the address bus. the falling edge of address strobe (adstb) is used to load these bits from the data lines to the latch. address enable (aen) is used to enable the bits onto the address bus through a three-state enable. the lower order address bits are output by the 82c37a directly. lines a0-a7 should be connected to the address bus. figure 12 shows the time relationships between clk, aen, adstb, db0-db7 and a0-a7. during block and demand transfer mode service, which include multiple transfers, the addresses generated will be sequential. for many transfers the data held in the external address latch will remain the same. this data need only change when a carry or borrow from a7 to a8 takes place in the normal sequence of addresses. to save time and speed transfers, the 82c37a executes s1 states only when updating of a8-a15 in the latch is necessary. this means for long services, s1 states and address strobes may occur only once every 256 transfers, a savings of 255 clock cycles for each 256 transfers. programming the 82c37a will accept programming from the host processor anytime that hlda is inactive, and at least one rising clock edge has occurred after hlda went low. it is the responsibility of the host to assure that programming and hlda are mutually exclusive. note that a problem can occur if a dma request occurs on an unmasked channel while the 82c37a is being pro- grammed. for instance, the cpu may be starting to repro- gram the two byte address register of channel 1 when channel 1 receives a dma request. if the 82c37a is enabled (bit 2 in the command register is 0), and channel 1 is unmasked, a dma service will occur after only one byte of the address register has been reprogrammed. this condi- tion can be avoided by disabling the controller (setting bit 2 in the command register) or masking the channel before programming any of its registers. once the programming is complete, the controller can be enabled/unmasked. after power-up it is suggested that all internal locations be loaded with some known value, even if some channels are unused. this will aid in debugging. register description current address register - each channel has a 16-bit current address register. this register holds the value of the address used during dma transfers. the address is auto- matically incremented or decremented by one after each transfer and the values of the address are stored in the cur- rent address register during the transfer. this register is writ- ten or read by the microprocessor in successive 8-bit bytes. see figure 6 for programming information. it may also be reinitialized by an autoinitialize back to its original value. autoinitialize takes place only after an eop. in memory-to- memory mode, the channel 0 current address register can be prevented from incrementing or decrementing by setting the address hold bit in the command register. 1st service 0 1 2 3 highest lowest 2nd service 2 3 0 1 service 3rd service 3 0 1 2 service request service
4-200 82c37a current word count register - each channel has a 16-bit current word count register. this register determines the number of transfers to be performed. the actual number of transfers will be one more than the number programmed in the current word count register (i.e., programming a count of 100 will result in 101 transfers). the word count is decremented after each transfer. when the value in the register goes from zero to ffffh, a tc will be generated. this register is loaded or read in successive 8-bit bytes by the microprocessor in the program condition. see figure 6 for programming information. following the end of a dma service it may also be reinitialized by an autoinitialization back to its original value. autoinitialization can occur only when an eop occurs. if it is not autoinitialized, this register will have a count of ffffh after tc. base address and base word count registers - each channel has a pair of base address and base word count registers. these 16-bit registers store the original value of their associated current registers. during autoinitialize these values are used to restore the current registers to their original values. the base registers are written simulta- neously with their corresponding current register in 8-bit bytes in the program condition by the microprocessor. see figure 6 for programming information. these registers can- not be read by the microprocessor. command register - this 8-bit register controls the opera- tion of the 82c37a. it is programmed by the microprocessor and is cleared by reset or a master clear instruction. the following diagram lists the function of the command register bits. see figure 4 for read and write addresses. mode register - each channel has a 6-bit mode register associated with it. when the register is being written to by the microprocessor in the program condition, bits 0 and 1 determine which channel mode register is to be written. when the processor reads a mode register, bits 0 and 1 will both be ones. see the following diagram and figure 4 for mode register functions and addresses. request register - the 82c37a can respond to requests for dma service which are initiated by software as well as by a dreq. each channel has a request bit associated with it in the 4-bit request register. these are non-maskable and subject to prioritization by the priority encoder network. each register bit is set or reset separately under software control. the entire register is cleared by a reset or master clear instruction. to set or reset a bit, the software loads the proper form of the data word. see figure 4 for register address coding, and the following diagram for request register format. a software request for dma operation can be made in block or single modes. for memory-to-memory transfers, the software request for channel 0 should be set. when reading the request register, bits 4-7 will always read as ones, and bits 0-3 will display the request bits of channels 0-3 respectively. command register 76543210 bit number 0 1 memory-to-memory disable memory-to-memory enable 0 1 x channel 0 address hold disable channel 0 address hold enable if bit 0 = 0 0 1 controller enable controller disable 0 1 x normal timing compressed timing if bit 0 = 1 0 1 fixed priority rotating priority 0 1 x late write selection extended write selection if bit 3 = 1 0 1 dreq sense active high dreq sense active low 0 1 dack sense active low dack sense active high mode register 76543210 bit number 00 01 10 11 xx channel 0 select channel 1 select channel 2 select channel 3 select readback 00 01 10 11 xx verify transfer write transfer read transfer illegal if bits 6 and 7 = 11 0 1 autoinitialization disable autoinitialization enable 0 1 address increment select address decrement select 00 01 10 11 demand mode select single mode select block mode select cascade mode select request register 76543210 bit number 00 01 10 11 select channel 0 select channel 1 select channel 2 select channel 3 0 1 reset request bit set request bit dont care, write bits 4-7 all ones, read
4-201 82c37a mask register - each channel has associated with it a mask bit which can be set to disable an incoming dreq. each mask bit is set when its associated channel produces an eop if the channel is not programmed to autoinitialize. each bit of the 4-bit mask register may also be set or cleared separately or simultaneously under software control. the entire register is also set by a reset or master clear. this disables all hard- ware dma requests until a clear mask register instruction allows them to occur. the instruction to separately set or clear the mask bits is similar in form to that used with the request register. refer to the following diagram and figure 4 for details. when reading the mask register, bits 4-7 will always read as logical ones, and bits 0-3 will display the mask bits of channels 0-3, respectively. the 4 bits of the mask register may be cleared simultaneously by using the clear mask reg- ister command (see software commands section). all four bits of the mask register may also be written with a single command. status register - the status register is available to be read out of the 82c37a by the microprocessor. it contains information about the status of the devices at this point. this information includes which channels have reached a terminal count and which channels have pending dma requests. bits 0-3 are set every time a tc is reached by that channel or an external eop is applied. these bits are cleared upon reset, master clear, and on each status read. bits 4-7 are set whenever their corresponding channel is requesting service, regardless of the mask bit state. if the mask bits are set, soft- ware can poll the status register to determine which channels have dreqs, and selectively clear a mask bit, thus allowing user de?ned service priority. status bits 4-7 are updated while the clock is high, and latched on the falling edge. status bits 4-7 are cleared upon reset or master clear. temporary register - the temporary register is used to hold data during memory-to-memory transfers. following the completion of the transfers, the last byte moved can be read by the microprocessor. the temporary register always contains the last byte transferred in the previous memory-to- memory operation, unless cleared by a reset or master clear. mask register 76543210 bit number 00 01 10 11 select channel 0 mask bit select channel 1 mask bit select channel 2 mask bit select channel 3 mask bit 0 1 clear mask bit set mask bit 76543210 bit number 0 1 clear channel 0 mask bit set channel 0 mask bit 0 1 clear channel 1 mask bit set channel 1 mask bit 0 1 clear channel 2 mask bit set channel 2 mask bit 0 1 clear channel 3 mask bit set channel 3 mask bit dont care dont care, write all ones, read status register 76543210 bit number 1 channel 0 has reached tc 1 channel 1 has reached tc 1 channel 2 has reached tc 1 channel 3 has reached tc 1 channel 0 request 1 channel 1 request 1 channel 2 request 1 channel 3 request operation a3 a2 a1 a0 ior io w read status register 100001 write command register 100010 read request register 100101 write request register 100110 read command register 101001 write single mask bit 101010 read mode register 101101 write mode register 101110 set first/last f/f 110001 clear first/last f/f 110010 read temporary register 110101 master clear 110110 clear mode reg. counter 111001 clear mask register 111010 read all mask bits 111101 write all mask bits 111110 figure 4. software command codes and register codes
4-202 82c37a software commands there are special software commands which can be executed by reading or writing to the 82c37a. these com- mands do not depend on the speci?c data pattern on the data bus, but are activated by the i/o operation itself. on read type commands, the data value is not guaranteed. these commands are: clear first/last flip-flop - this command is executed prior to writing or reading new address or word count infor- mation to the 82c37a. this command initializes the ?ip-?op to a known state (low byte ?rst) so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence. set first/last flip-flop - this command will set the ?ip-?op to select the high byte ?rst on read and write operations to address and word count registers. master clear - this software instruction has the same effect as the hardware reset. the command, status, request, and temporary registers, and internal first/last flip-flop and mode register counter are cleared and the mask register is set. the 82c37a will enter the idle cycle. clear mask register - this command clears the mask bits of all four channels, enabling them to accept dma requests. clear mode register counter - since only one address location is available for reading the mode registers, an inter- nal two-bit counter has been included to select mode regis- ters during read operation. to read the mode registers, ?rst execute the clear mode register counter command, then do consecutive reads until the desired channel is read. read order is channel 0 ?rst, channel 3 last. the lower two bits on all mode registers will read as ones. external eop operation the eop pin is a bidirectional, open drain pin which may be driven by external signals to terminate dma operation. because eop is an open drain pin an external pull-up resis- tor to v cc is required. the value of the external pull-up resistor used should guarantee a rise time of less than 125ns. it is important to note that the 82c37a will not accept external eop signals when it is in a si (idle) state. the controller must be active to latch ext eop. once latched, the ext eop will be acted upon during the next s2 state, unless the 82c37a enters an idle state ?rst. in the latter case, the latched eop is cleared. external eop pulses occurring between active dma transfers in demand mode will not be recognized, since the 82c37a is in an si state. channel register operation signals first/last flip-flop state data bus db0-db7 cs ior io wa3a2a1a0 0 base and current address write 0100000 0 a0-a7 0100000 1 a8-a15 current address read 0010000 0 a0-a7 0010000 1 a8-a15 base and current word count write 0100001 0 w0-w7 0100001 1 w8-w15 current word count read 0010001 0 w0-w7 0010001 1 w8-w15 1 base and current address write 0100010 0 a0-a7 0100010 1 a8-a15 current address read 0010010 0 a0-a7 0010010 1 a8-a15 base and current word count write 0100011 0 w0-w7 0100011 1 w8-w15 current word count read 0010011 0 w0-w7 0010011 1 w8-w15 2 base and current address write 0100100 0 a0-a7 0100100 1 a8-a15 current address read 0010100 0 a0-a7 0010100 1 a8-a15 base and current word count write 0100101 0 w0-w7 0100101 1 w8-w15 current word count read 0010101 0 w0-w7 0010101 1 w8-w15 3 base and current address write 0100110 0 a0-a7 0100110 1 a8-a15 current address read 00101100 a0-a7 00101101 a8-a15 base and current word count write 01001110 w0-w7 01001111 w8-w15 current word count read 00101110 w0-w7 00101111 w8-w15 figure 5. word count and address register command codes
4-203 82c37a application information figure 6 shows an application for a dma system utilizing the 82c37a dma controller and the 80c88 microprocessor. in this application, the 82c37a dma controller is used to improve system performance by allowing an i/o device to transfer data directly to or from system memory. components the system clock is generated by the 82c84a clock driver and is inverted to meet the clock high and low times required by the 82c37a dma controller. the four or gates are used to support the 80c88 microprocessor in minimum mode by producing the control signals used by the processor to access memory or i/o. a decoder is used to generate chip select for the dma controller and memory. the most signi?- cant bits of the address are output on the address/data bus. therefore, the 82c82 octal latch is used to demultiplex the address. hold acknowledge (hlda) and address enable (aen) are ored together to insure that the dma controller does not have bus contention with the microprocessor. operation a dma request (dreq) is generated by the i/o device. after receiving the dma request, the dma controller will issue a hold request (hrq) to the processor. the system busses are not released to the dma controller until a hold acknowl- edge signal is returned to the dma controller from the 80c88 processor. after the hold acknowledge has been received, addresses and control signals are generated by the dma controller to accomplish the dma transfers. data is transferred directly from the i/o device to memory (or vice versa) with ior and memw (or memr and io w) being active. note that data is not read into or driven out of the dma controller in i/o-to-memory or memory-to-i/o data transfers. figure 6. application for dma system memr memw ior io w memcs memr memw memory 47k w v cc address bus data bus v cc data bus 80c88 wr rd m/ io hrq hlda ax ale ad0 ad7 mn/ mx clk 82c84a or 82c85 hlda memcs stb 82c82 oe decoder address bus stb 82c82 oe a0-7 cs clk eop hlda ior dack adstb aen db0-7 io w memr memw hrq dreq0 82c37a ior io w v cc cs dreq i/o device note: the address lines need pull-up resistors.
4-204 82c37a figure 7 shows an application for a dma system using the 82c37a dma controller and the 80c286 microprocessor. in this application, the system clock comes from the 82c284 clock generator pclk signal which is inverted to provide proper ready setup and hold times to the dma controller in an 80c286 system. the read and write signals from the dma controller may be wired directly to the read/write con- trol signals from the 82c288 bus controller. the octal latch for a8-a15 from the dma controllers data bus is on the local 80c286 address bus so that memory chip selects may still be generated during dma transfers. the transceiver on a0- a7 is controlled by aen and is not necessary, but may be used to drive a heavily loaded system address bus during transfers. the data bus transceivers simply isolate the dma controller from the local microprocessor bus and allow pro- gramming on the upper or lower half of the data bus. figure 7. 80c286 dma application memw memr memcs memory a0 - a23 io w dack i/o ior system bus a0 - a7 transceiver oe t/ r device dreq cs d0 - d15 trans- ceiver trans- ceiver latch stb oe aen d0-d7 v cc a0-a7 ior io w memr memw dack 0-3 d0-d7 dreq 0-3 eop aen adstb hrq hlda clk ready 82c37a ior io w memr memw to corresponding 82c288 signals and memory/peripherals d8 - d15 transceiver latch d0 - d7 a8 - a15 decode chip select to memory/ peripherals 80c286 a0-a23 d0-d15 read y hld hlda clk iorc io wc mrdc mwtc ior io w memr memw clk 82c288 82c284 clk pclk read y
4-205 82c37a absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range c82c37a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c i82c37a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c m82c37a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c thermal resistance (typical) q ja ( o c/w) q jc ( o c/w) cerdip package . . . . . . . . . . . . . . . . 50 10 clcc package . . . . . . . . . . . . . . . . . . 65 14 pdip package . . . . . . . . . . . . . . . . . . . 50 n/a plcc package . . . . . . . . . . . . . . . . . . 46 n/a storage temperature range . . . . . . . . . . . . . . . . . .-65 o c to +150 o c maximum junction temperature ceramic package . . . . . . . +175 o c maximum junction temperature plastic package. . . . . . . . . +150 o c maximum lead temperature package (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 o c (plcc - lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2325 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. dc electrical speci?cations v cc = +5.0 10%, t a = 0 o c to +70 o c (c82c37a) t a = -40 o c to +85 o c (i82c37a) t a = -55 o c to +125 o c (m82c37a) symbol parameter min max units test conditions vih logical one input voltage 2 - v c82c37a, i82c37a 2.2 - v m82c37a vil logical zero input voltage - 0.8 v vihc clk input logical one voltage v cc -0.8 - v vilc clk input logical zero voltage - 0.8 v voh output high voltage 3.0 - v ioh = -2.5ma v cc -0.4 - v ioh = -100 m a vol output low voltage - 0.4 v iol = +2.5ma all output except eop, iol = +3.2ma for eop pin 36 only. ii input leakage current -1 +1 m a vin = gnd or v cc , pins 6, 7, 11-13, 16-19 io output leakage current -10 +10 m a vout = gnd or v cc , pins 1-4, 21-23, 26-30, 32-40 iccsb standby power supply current -10 m av cc = 5.5v, vin = v cc or gnd, outputs open iccop operating power supply current - 2 ma/mhz v cc = 5.5v, clk freq = maximum, vin = v cc or gnd, outputs open capacitance t a = +25 o c symbol parameter typ units test conditions cin input capacitance 25 pf freq = 1mhz, all measurements are referenced to device gnd cout output capacitance 40 pf ci/o i/o capacitance 25 pf
4-206 82c37a ac electrical speci?cations v cc = +5.0v 10%, gnd = 0v, t a = 0 o c to +70 o c (c82c37a), t a = -40 o c to +85 o c (i82c37a), t a = -55 o c to +125 o c (m82c37a) symbol parameter 82c37a-5 82c37a 82c37a-12 units min max min max min max dma (master) mode (1)tael aen high from clk low (s1) delay time - 175 - 105 - 50 ns (2)taet aen low from clk high (si) delay time - 130 - 80 - 50 ns (3)tafab adr active to float delay from clk high -90-55-55ns (4)tafc read or write float delay from clk high - 120 - 75 - 50 ns (5)tafdb db active to float delay from clk high - 170 - 135 - 90 ns (6)tahr adr from read high hold time tcy-100 - tcy-75 - tcy-65 - ns (7)tahs db from adstb low hold time tcl-18 - tcl-18 - tcl-18 - ns (8)tahw adr from write high hold time tcy-65 - tcy-65 - tcy-50 - ns (9)tak dack valid from clk low delay time - 170 - 105 - 69 ns eop high from clk high delay time - 170 - 105 - 90 ns eop low from clk high delay time - 100 - 60 - 35 ns (10)tasm adr stable from clk high - 110 - 60 - 50 ns (11)tass db to adstb low setup time tch-20 - tch-20 - tch-20 - ns (12)tch clk high time (transitions 10ns) 70 - 55 - 30 - ns (13)tcl clk low time (transitions 10ns) 50 - 43 - 30 - ns (14)tcy clk cycle time 200 - 125 - 80 - ns (15)tdcl clk high to read or write low delay - 190 - 130 - 120 ns (16)tdctr read high from clk high (s4) delay time - 190 - 115 - 80 ns (17)tdctw write high from clk high (s4) delay time - 130 - 80 - 70 ns (18)tdq hrq valid from clk high delay time - 120 - 75 - 30 ns (19)teph eop hold time from clk low (s2) 90 - 90 - 50 - ns (20)teps eop low to clk low setup time 40 - 25 - 0 - ns
4-207 82c37a (21)tepw eop pulse width 220 - 135 - 50 - ns (22)tfaab adr valid delay from clk high - 110 - 60 - 50 ns (23)tfac read or write active from clk high - 150 - 90 - 50 ns (24)tfadb db valid delay from clk high - 110 - 60 - 45 ns (25)ths hlda valid to clk high setup time 75 - 45 - 10 - ns (26)tidh input data from memr high hold time 0-0-0-ns (27)tids input data to memr high setup time 155 - 90 - 45 - ns (28)todh output data from memw high hold time 15 - 15 - tcy-50 - ns (29)todv output data valid to memw high tcy-35 - tcy-35 - tcy-10 - ns (30)tqs dreq to clk low (si, s4) setup time 0-0-0-ns (31)trh clk to ready low hold time 20 - 20 - 10 - ns (32)trs ready to clk low setup time 60 - 35 - 15 - ns (33)tclsh adstb high from clk low delay time -80-70-70ns (34)tclsl adstb low from clk low delay time - 120 - 120 - 60 ns (35)twrrd read high delay from write high 0 - 0 - 5 - ns (36)trlrh read pulse width, normal timing 2tcy-60 - 2tcy-60 - 2tcy-55 - ns (37)tshsl adstb pulse width tcy-80 - tcy-50 - tcy-35 - ns (38)twlwha extended write pulse width 2tcy-100 - 2tcy-85 - 2tcy-80 - ns (39)twlwh write pulse width tcy-100 - tcy-85 - tcy-80 - ns (40)trlrhc read pulse width, compressed tcy-60 - tcy-60 - tcy-55 - ns (56)tavrl adr valid to read low 17 - 17 - 17 - ns (57)tavwl adr valid to write low 7 - 7 - 7 - ns (58)trhal read high to aen low 15 - 15 - 15 - ns (59)trhsh read high to adstb high 13 - 13 - 13 - ns (60)twhsh write high to adstb high 15 - 15 - 15 - ns (61)tdvrl dack valid to read low 25 - 25 - 25 - ns ac electrical speci?cations v cc = +5.0v 10%, gnd = 0v, t a = 0 o c to +70 o c (c82c37a), t a = -40 o c to +85 o c (i82c37a), t a = -55 o c to +125 o c (m82c37a) (continued) symbol parameter 82c37a-5 82c37a 82c37a-12 units min max min max min max
4-208 82c37a (62)tdvwl dack valid to write low 25 - 25 - 25 - ns (63)trhdi read high to dack inactive 12 - 12 - 12 - ns (64)tazrl adr float to read low -2.5 - -2.5 - -2.5 - ns peripheral (slave) mode (41)tar adr valid or cs low to read low 10 - 10 - 0 - ns (42)tawl adr valid to write low setup time 0 - 0 - 0 - ns (43)tcwl cs low to write low setup time 0 - 0 - 0 - ns (44)tdw data valid to write high setup time 150 - 100 - 60 - ns (45)tra adr or cs hold from read high 0 - 0 - 0 - ns (46)trde data access from read - 140 - 120 - 80 ns (47)trdf db float delay from read high 5 85 5 85 5 55 ns (48)trstd power supply high to reset low setup time 500 - 500 - 500 - ns (49)trsts reset to first ior or io w 2tcy - 2tcy - 2tcy - ns (50)trstw reset pulse width 300 - 300 - 300 - ns (51)trw read pulse width 200 - 155 - 85 - ns (52)twa adr from write high hold time 0 - 0 - 0 - ns (53)twc cs high from write high hold time 0-0-0-ns (54)twd data from write high hold time 10 - 10 - 10 - ns (55)twws write pulse width 150 - 100 - 45 - ns ac electrical speci?cations v cc = +5.0v 10%, gnd = 0v, t a = 0 o c to +70 o c (c82c37a), t a = -40 o c to +85 o c (i82c37a), t a = -55 o c to +125 o c (m82c37a) (continued) symbol parameter 82c37a-5 82c37a 82c37a-12 units min max min max min max
4-209 82c37a timing waveforms figure 8. slave mode write note: successive write accesses to the 82c37a must allow at least tcy as recovery time between accesses. a tcy recovery time must be allowed before executing a write access after a read access. figure 9. slave mode read note: successive read accesses to the 82c37a must allow at least tcy as recovery time between accesses. a tcy recovery time must be allowed before executing a read access after a write access. cs a0 - a3 io w db0 - db7 input valid input valid twws (55) tdw (44) tcwl (43) tawl (42) twc (53) twa (52) twd (54) cs a0 - a3 ior db0 -db7 address must be valid tar (41) trde (46) trdf (47) tra (45) trw (51) data out valid
4-210 82c37a figure 10. dma transfer timing waveforms (continued) tepw (21) tak (9) si si tqs (30) s0 s0 s1 s2 s3 s4 s2 s3 s4 si si si tdq (18) ths (25) tael (1) tclsh (33) tqs (30) tcl (13) tcy (14) tch (12) tdq (18) taet (2) tshsl (37) tclsl (34) teps (20) teph (19) trhal (58) tak (9) tafab (3) tahw (8) tahr (6) trhdi (63) tafc (4) tdctr (16) tdcl (15) clk dreq hrq hlda aen adstb db0-db7 a0-a7 dack read write int eop ext eop (64) tazrl tafdb (5) tfaab (22) tfadb (24) tass (11) tahs (7) a8-a15 tak (9) tdcl (15) tfac (23) tdcl (15) tdvwl (62) twlwha (38) tdctw (17) tavwl (57) tdval (61) (for extended write) (for extended write) tak (9) tdcl (15) twlwh (39) tdctw (17) twrrd (35) tavrl (56) trlrh (36) tdctr (16) tahr (6) tahw (8) tasm (10) address valid address valid
4-211 82c37a figure 11. memory-to-memory transfer figure 12. ready note: ready must not transition during the speci?ed setup and hold times. timing waveforms (continued) s0 (33) tclsh clk s11 s12 s13 s14 s21 s22 s23 s24 s11/si adstb a0-a7 db0-db7 memr memw eop ext eop (34) tclsl (7) tahs tfaab (22) tass (11) tfadb (24) (5) tafdb in a8-a15 (16) tdctr tfac (23) tfac (23) address valid address valid (33) tclsh (34) tclsl twhsh (60) tclsh (33) tafab (3) tafc (4) tafc (4) (59) trhsh tahs (7) a8-a15 (24) tfadb tidh (26) tids (27) tafdb (5) tdcl (15) tdcl (15) tdctw (17) tak (9) tak (9) out tepw (21) teps (20) (19) teph extended write tovd (29) todh (28) tazrl (64) tdcl (15) tass (11) clk extended write (16) tdctr s4 sw sw s3 s2 (15) tdcl (15) tdcl (15)tdcl (31)trh (32)trs trh (32)trs (17) tdctw read write ready (31)
4-212 82c37a ac test circuits ac testing input, output waveforms figure 13. compressed transfer figure 14. reset timing waveforms (continued) clk s4 s2 (10) tasm (15) tdcl trlrhc (40) tdctr (16) tdcl (15) (10) tasm tdctr (16) tdctw (17) trh (31) trs (32) s2 s4 trs (32) trh (31) tdctw (17) a0-a7 read write ready valid valid (48) trstd (50) trstw (49) trsts ior or io w reset v cc test condition definition table pins v1 r1 c1 all outputs except eop 1.7v 520 w 100pf eop v cc 1.6k w 50pf test point r1 v1 c1 (note) output from device under test note: includes stray and fixture capacitance note: ac testing: all ac parameters tested as per test circuits. input rise and fall times are driven at ins/v. clk input must switch between vihc +0.4v and vilc -0.4v voh vo -0.45 0.45 vol output l or h ? z voh 2.0v 0.8v vol input z ? l or h vih + 0.4v vil - 0.4v 1.5v 1.5v voh vol output output
4-213 82c37a burn-in circuits md82c37a cerdip mr82c37a clcc notes: 1. v cc = 5.5v 0.5v 2. vih = 4.5v 10% 3. vil = -0.2v to 0.4v 4. gnd = 0v 5. r1 = 1.2k w 5% 6. r2 = 47k w 5% 7. c1 = 0.01 m f minimum 8. c2 = 0.1 m f minimum 9. d1 = 1n4002 10. f0 = 100khz 10% 11. f1 = f0/2, f2 = f1/2,..., f15 = f14/2 12. do0 - do6 are outputs from the 82c82 octal latching bus driver do5 vcc/2 vcc/2 vcc/2 a do5 vcc/2 vcc/2 vcc/2 do5 f1 do6 vcc/2 f12 f13 f14 f15 gnd vcc 33 34 35 36 37 38 40 32 31 30 29 24 25 26 27 28 21 22 23 13 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 39 1 vcc/2 vcc/2 vcc/2 a vcc do1 vcc do0 b do2 do3 do4 f10 vcc/2 vcc/2 f8 do4 f7 vcc/2 vcc/2 f9 r1 r1 r1 r1 r1 r1 r2 r1 r2 r2 r2 r2 r2 r2 r1 r1 r2 r2 r2 r1 r2 r1 r1 r1 r1 r3 r1 r1 r1 r2 r2 r2 r2 r1 r1 r1 r1 r1 vcc/2 vcc/2 f8 f14 f13 f12 vcc/2 f15 gnd do4 open do5 vcc/2 vcc/2 do5 f1 d06 vcc/2 open vcc/2 14 13 12 11 10 9 8 7 17 16 15 2 5 30 35 39 38 37 36 33 34 32 31 29 4 6 3 1 40 41 42 43 44 a vcc/2 vcc/2 vcc/2 vcc/2 vcc/2 vcc/2 a v cc do1 b do2 do3 do4 f10 f9 v cc vcc/2 v cc do5 open open do4 28 27 26 25 24 23 22 21 20 19 18 v cc v cc d1 c1 c1 ab
4-214 die characteristics die dimensions: 148 x 159 x 19 1mils (3760- x 4040 x 525 m m) metallization: type: sialcu thickness: metal 1: 8k ? 0.75k ? thickness: metal 2: 12k ? 1.0k ? glassivation: type: nitrox thickness: 10k ? 3k ? worst case current density: 0.6 x 10 5 a/cm 2 metallization mask layout 82c37a 82c37a

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